1. Field of the Invention
The present invention relates to a layout structure for a semiconductor device, and more particularly relates to a layout structure capable of independent supply of a substrate or well potential from a power supply potential.
2. Description of the Related Art
In recent years, reduction in stand-by current in an LSI using MOS (metal oxide semiconductor) transistors has been an important issue. However, due to reduction in process size and reduction in threshold voltage resulting from the development of low voltage LSIs, leakage currents in transistors in OFF state have been increased to a nonnegligible level.
To cope with such problems, there has been a known method in which a leakage current in a transistor is reduced by setting a substrate or well potential at a different level from a source potential so that a threshold voltage is set to be apparently high. In this method, a substrate potential is set to be lower than a source potential in an n-type transistor and a substrate potential is set to be higher than a source potential in a p-type transistor. Moreover, to use this method, in an LSI design using automatic placing and routing, it is necessary to make it possible to set a substrate or well potential at a different level from a source potential in cell data contained in a standard cell library.
FIGS. 12A through 12E are views illustrating an exemplary known cell layout structure which is configured so that a substrate or well potential can be supplied independently from a power supply potential. FIG. 12A is a plan view of the known cell layout structure. FIGS. 12B through 12E are cross-sectional views of the layout structure of FIG. 12A.
In the structure shown in FIGS. 12A through 12E, a VDD wire 150 and a VSS wire 151 are provided in a first wiring layer for wiring in cells and a second wiring layer formed above the first wiring layer. A substrate or well potential of a PMOS TP15 is supplied from a high concentration n-type impurity doped region 152 located above a PMOS substrate or an n-well but is not supplied from the VDD wire 150. A substrate or well potential of a NMOS TN15 is supplied from a high concentration p-type impurity doped region 153 located above an NMOS substrate or a p-well but is not supplied from the VSS wire 151. In the layout structure of FIGS. 12A through 12E, the substrate or well potential is supplied only by the impurity doped region. Compared to a wiring layer, an impurity doped region has a higher sheet resistance by one or more orders of magnitude and therefore a potential drop easily occurs. Accordingly, a substrate or well potential is not stable and a threshold in a transistor fluctuates, or like inconvenience occurs. This causes problems such as reduction in reliability of an LSI operation, insufficient suppression of a stand-by leakage current and the like.
To avoid the above-described problems, a method using a reinforcing power supply cell shown in FIGS. 13A through 13E has been proposed (disclosed in Patent References 1 and 2). FIG. 13A is a plan view of the layout structure and FIGS. 13B through 13E are cross-sectional views of the layout structure of FIG. 13A. In this proposal, the reinforcing power supply cell of FIGS. 13A through 13E and a cell having the layout structure of FIGS. 12A through 12E are combined and arranged, for example, in the manner shown in FIG. 14. Thus, reinforcing power supply for a substrate or well potential can be performed through a wire 160 and a wire 161 of FIGS. 13A through 13E provided in a first wiring layer and a second wiring layer. Therefore, a stable potential can be supplied as a substrate or well potential independently from a power supply potential.    (Patent Reference 1) Japanese Patent No. 3672788    (Patent Reference 2) Japanese Laid-Open Publication No. 2003-309178    (Patent Reference 3) Japanese Laid-Open Publication No. 2001-148464
However, the known layout structure has the following problems.
In the layout structure of FIGS. 12A through 12E, FIGS. 13A through 13E and FIGS. 14A through 14E, power is supplied simultaneously to a substrate or well at a high potential (NWVDD) side and a substrate or well at a low potential (PWVDD) side through the reinforcing power supply cell. However, it has become clear that as the process size has been reduced, a maximum effect of reduction of a leakage current by controlling a substrate or well potential can not be necessarily achieved when both of the NWVDD side and the PWVSS side are simultaneously controlled, and there are cases where a greater effect can be achieved by controlling only one of the NWVDD side and the PWVSS side.
More detail explanation on this will be given below. As shown in a schematic view of an NMOS of FIGS. 15A and 15B, leakage currents are divided roughly into three groups: (1) sub-threshold leakage current flowing from a drain to a source when a transistor is in a non-conductive state; (2) junction leakage current flowing from a drain to a substrate by interband tunneling when a transistor is in a non-conductive state; and (3) gate leakage current tunneling though a gate insulating film and flowing from a gate electrode to a source and a drain via an inversion layer when a transistor is in a conductive state. A leakage current in an LSI is a total sum of the three currents. To control a sub-threshold leakage current of those three, a so-called “substrate control technique” has been introduced. The substrate control technique is a technique in which a bias voltage is applied to a substrate terminal of a transistor to control a threshold voltage. Specifically, application of a bias voltage in the direction in which carries flow less easily is referred to as “reverse body bias (RBB)”. To reduce a sub-threshold leakage current, application of a bias by RBB is effective. It is considered that the larger a bias amount is, the greater the effect of reduction of a sub-threshold leakage current is.
As a type of junction leakage current, there is a current called GIDL (gate induced drain leakage) flowing when a high electric field is applied to a region located in the vicinity of a drain and close to a gate. A GIDL current is characterized in that it is increased by increasing bias application by RBB. Due to recent reduction in process size, control of electric field in the region located in the vicinity of a drain and close to a gate is more difficult, and therefore, the ratio of a GIDL current to a leakage current is now nonnegligible.
Thus, a sub-threshold leakage current and a GIDL current (junction leakage current) is in the relationship in which by increasing bias application by RBB, the sub-threshold leakage current is reduced but the GIDL current is increased. Therefore, to minimize a leakage current, the known method in which RBB is merely set to be large is not proper and it is necessary to assess an optimum level and then set RBB. For example, depending on transistor characteristics, there might be cases where the GIDL current (junction leakage current) after the increase is larger than the sub-thread leakage current which can be reduced by performing substrate control. In such a case, a leakage current can not be reduced. For the above-described reason, it is understood that there are cases where a greater effect of reduction in leakage current can be achieved by controlling only one of the NWVDD side and the PWVSS side.
In such a case, the reinforcing power supply cell arranged originally for the purpose of supplying, as a substrate or well potential, a different potential from a power supply potential can be used to supply, as a substrate or well potential, the same potential as the power supply potential, thereby achieving a desired leakage current reduction effect. For example, in FIGS. 13A through 13E, a VDD wire 162 and the wire (which will be hereafter referred to as a “NWVDD wire”) 160 for reinforcing power supply for the substrate or well potential on the NWVDD side are connected to one another in the second wiring layer. Thus, a potential power supply potential and the substrate or well potential at the NWVDD side can be made to be the same potential. However, in this method, a wiring region of the second wiring layer in the reinforcing power supply cell is wastefully used and thus increase in chip area is caused.
To further reduce a layout area of a semiconductor device, a reinforcing power supply cell having a layout structure which achieve the same effects as those of the reinforcing power supply cell of FIGS. 13A through 13E and exhibits high wiring efficiency has to be obtained.
Moreover, to further reduce a layout area of a semiconductor device, it is preferable that the object of supplying, as a substrate or well potential, a stable potential independently from a power supply potential is achieved and, at the same time, the number of reinforcing power supply cells to be arranged is reduced as small as possible.